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Elements of Verification from SOCcentral

Posted in Hardware Engineering, Links, Technology by engtech on May 14, 2006

This is a pretty decent high-level document describing the modern (2005/03) methods of verification. It would probably be good for introducing someone to verification, although there isn’t enough depth to give a good feel for what everything is.

It describes:

  • Functional verification
  • Conventional Verification (BFM based, directed testing)
  • Hardware verification language (HVL) based verification (constrained random, coverage driven)
  • VIP-based verification (treating verification components as reusable IP)
  • Layered, object-oriented verification methodology for next generation SoCs (getting into reuse methodologies like eRM/RVM/VMM/AVM, although none are specifically mentioned)
  • Assertion-based verification (design for verification)
  • Formal verification (equivalency checking, formal RTL verification)

What is left out:

  • Gate-level verification
  • Wafer testing
  • Chip bring-up verification
  • Manufacturing verification

SOCcentral: Elements of Verification (SOCcentral 12420)

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