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SystemVerilog reference verification methodology // EETimes.com

Posted in Hardware Engineering, Links, Technology by engtech on May 07, 2006

This article gives an overview of the Verification Methodology Manual (VMM) developed by Synopsys and ARM. I have the book, it is quite good. They discuss the various layers of a verification environment

Test Testcase
Scenario Generator; Functional Coverage
Functional Driver Self-Check Monitor
Command Checker Checker
Signal DUT

The advantage to the layered approaches is that the interfaces between layers are well defined and the components in a layer can be swapped and replaced without affecting the other layers. Only the test layer needs to be modified to generate a new test. The principal idea behind re-usability is having well-defined interfaces so that components can be switched.

It discussions top-down versus bottom-up approaches. In a top-down approach verification engineers build testbench as a stand-alone self-checking environment. In a bottom-up approach design engineers build block-level pin/cycle-based test-harnesses and then work their way up to a transaction-based environment.

EETimes.com – SystemVerilog reference verification methodology: RTL

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