This is an article by Richard Newell and Rindert Schutten discussing Design-for-Verification (DFV) using assertions in SystemVerilog. The focus is on hardware acceleration flows and how to use assert/assume/cover in a synthesizable manner so that the hardware acceleration can function in near real-time. The idea is that there are signals feeding back from the synthesized assertions to the software simulator using SCE-MI.
They give these four guidelines when writing assertions to ensure that they are synthesizable:
Guideline 1: In assert statements, do not use a pass statement. Use only the else statement, since this indicates an error condition.
Guideline 2: Ignore assertion control statements when implementing the assertions in hardware unless false failures need to be suppressed.
Guideline 3: Do not implement cover statement accounting functions in hardware-assisted verification; rely on pure software simulation to get this important information for debugging purposes.
Guideline 4: In cover statements, use a pass statement only if it is expected to be executed a few times during the simulation.
They also recommend writing synthesizable transactors so that the bulk of the transactor is on the hardware accelerator.
EETimes.com – Bringing assertions into hardware-assisted verification